This data is synchronized with the clock CLK. Note the serial data 1011 pattern presented at the SI input. The shift register has been cleared prior to any data by CLR’, an active low signal, which clears all type D Flip-Flops within the shift register. See waveforms below for above shift register. It is not practical to offer a 64-bit serial-in, parallel-out shift register requiring that many output pins. Note that serial-in, serial-out shift registers come in bigger than 8-bit lengths of 18 to 64-bits. The answer is that they actually only offer the serial-in, parallel-out shift register, as long as it has no more than 8-bits. If a serial-in, parallel-out shift register is so similar to a serial-in, serial-out shift register, why do manufacturers bother to offer both types? Why not just offer the serial-in, parallel-out shift register? Therefore, a serial-in, parallel-out shift register converts data from serial format to parallel format. It is different in that it makes all the internal stages available as outputs. Serial-in, Serial-out Shift RegisterĪ serial-in, parallel-out shift register is similar to the serial-in, serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. An Example of Using Serial-in, Parallel-out Shift Register.
